1 of 7 111899 features super-low power version of ds1232 50 a quiescent current halts and restarts an out-of-control microprocessor automatically restarts microprocessor after power failure monitors pushbutton for external override accurate 5% or 10% microprocessor power supply monitoring 8-pin dip, 8-pin soic or space saving -sop package available optional 16-pin soic package available industrial temperature -40c to +85c available, designated n pin assignment pin description pbrst - pushbutton reset input td - time delay set tol - selects 5% or 10% v cc detect gnd - ground rst - reset output (active high) rst - reset output (active low, open drain) st - strobe input v cc - +5 volt power description the DS1232LP/lps low power micromonitor chip monitors three vital conditions for a microprocessor: power supply, software execution, and external over-ride. first, a precision temperature- compensated reference and comparator circuit monitors the status of v cc . when an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces reset to the active state. when v cc returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. DS1232LP/lps low power micromonitor chip www.dalsemi.com DS1232LP 8-pin dip (300-mil) see mech. drawings section pbrst td tol gnd v cc st rst 1 2 3 4 8 7 6 5 rst DS1232LPs 16-pin soic (300-mil) see mech. drawings section nc pbrst nc td nc tol nc gnd nc vcc nc st nc rst nc rst 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 DS1232LP pbrst td tol gnd v cc st rst rst DS1232LPs-2 8-pin soic (150-mil) see mech. drawings section pbrst td tol gnd vcc st rst 1 2 3 4 8 7 6 5 rst 8 7 6 5 1 2 3 4
DS1232LP/lps 2 of 7 the second function the DS1232LP/lps performs is pushbutton reset control. the DS1232LP/lps debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. the third function is a watchdog timer. the DS1232LP/lps has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. the watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds. operation - power monitor the DS1232LP/lps detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. when v cc falls below a preset level as defined by tol, the v cc comparator outputs the signals rst and rst . when tol is connected to ground, the rst and rst signals become active as v cc falls below 4.75 volts. when tol is connected to v cc , the rst and rst signals become active as v cc falls below 4.5 volts. the rst and rst are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid v cc . on power-up, rst and rst are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize. operation - pushbutton reset the DS1232LP/lps provides an input pin for direct connection to a pushbutton (figure 1). the pushbutton reset input requires an active low signal. internally, this input is debounced and timed such that rst and rst signals of at least 250 ms minimum are generated. the 250 ms delay starts as the pushbutton reset input is released from low level. operation - watchdog timer the watchdog timer function forces rst and rst signals to the active state when the st input is not stimulated for a predetermined time period. the time period is set by the td input to be typically 150 ms with td connected to ground, 600 ms with td left unconnected, and 1.2 seconds with td connected to v cc . the watchdog timer starts timing out from the set time period as soon as rst and rst are inactive. if a high-to-low transition occurs on the st input pin prior to timeout, the watchdog timer is reset and begins to timeout again. if the watchdog timer is allowed to timeout, then the rst and rst signals are driven to the active state for 250 ms minimum. the st input can be derived from microprocessor address signals, data signals, and/or control signals. when the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. to guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in table 1. a typical circuit example is shown in figure 2.
DS1232LP/lps 3 of 7 micromonitor block diagram pushbutton reset figure 1 watchdog timer figure 2
DS1232LP/lps 4 of 7 timing diagram: pushbutton reset figure 3 timing diagram: strobe input figure 4 watchdog time-outs table 1 time-out td min typ max gnd 62.5 ms 150 ms 250 ms float 250 ms 600 ms 1000 ms v cc 500 ms 1200 ms 2000 ms
DS1232LP/lps 5 of 7 timing diagram: power-down figure 5 timing diagram: power-up figure 6
DS1232LP/lps 6 of 7 absolute maximum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground -0.5v to v cc + 0.5v operating temperature 0c to 70c operating temperature (industrial version) -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 st and pbrst input high level v ih 2.0 v cc +0.3 v 1 st and pbrst input low level v il -0.3 +0.8 v 1 dc electrical characteristics (0 c to 70 c; v cc =4.5 to 5.5v) parameter symbol min typ max units notes input leakage i il -1.0 +1.0 a 3 output current @ 2.4v i oh -8 -10 ma 5 output current @ 0.4v i ol 10 ma low level @ rst v ol 0.4 v 1 output voltage @ -500 ua v oh v cc -0.5v v cc -0.1v v 1, 7 output current (cmos) i cc1 50 a 2 operating current (ttl) i cc2 200 500 a 8 v cc trip point (tol=gnd) v cctp 4.50 4.62 4.74 v 1 v cc trip point (tol=v cc )v cctp 4.25 4.37 4.49 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf
DS1232LP/lps 7 of 7 ac electrical characteristics (0 c to 70 c; v cc =5v 10%) parameter symbol min typ max units notes pbrst = v il t pb 20 ms reset active time t rst 250 610 1000 ms st pulse width t st 20 ns 6, 9 v cc fail detect to rst and rst t rpd 50 175 s v cc slew rate 4.75v to 4.25v t f 300 s v cc detect to rst and rst inactive t rpu 250 610 1000 ms 4 v cc slew rate 4.25v to 4.75v t r 0ns pbrst stable low to rst and rst t pdly 20 ms notes: 1. all voltages referenced to ground. 2. measured with outputs open and st and pbrst within 0.5v of supply rails. 3. pbrst is internally pulled up to v cc with an internal impedance of 40k typical. 4. t r = 5 s. 5. rst is an open-drain output. 6. must not exceed t td minimum. see table 1. 7. rst remains within 0.5v of v cc on power-down until v cc drops below 2.0v. rst remains within 0.5v of gnd on power-down until v cc drops below 2.0v. 8. measured with outputs open and st and pbrst at ttl levels. 9. watchdog can not be disabled. it must be strobed to avoid resets. marking information: 8-pin dip - ?ds1232l? 16-pin soic - ?ds1232l? 8-pin soic - ?ds1232l? 8-pin -sop - ?1232?
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